Memory array devices, e.g., Static Random Access Memory (SRAM), may be used in digital computer systems to store and retrieve electronic data at highs speeds. Each item of data in memory arrays, called a bit, is stored in a separate circuit or device commonly referred to as a “cell.” Since computers use binary format to represent data, each cell can store one of two possible values (on or off). A typical memory array comprises millions of bits organized as an array consisting of horizontal rows and vertical columns. Each cell shares electrical connections with the other cells in its row and column. The horizontal lines connected to all cells in a row are called word lines, and the vertical lines (along which data flows into and out of the cell) are called data or bit lines. Cells are therefore accessed by proper selection of the word and bit lines.
Power consumption of a memory array may be made up of two components, dynamic power consumption and leakage power consumption. Dynamic power consumption relates to the power that is consumed when a particular word line is accessed to read from or write data to a cell. In an SRAM, only one particular word line is accessed at a particular time. The leakage power consumption may occur when a cell is not accessed but power continues to be consumed based on the leakage current which flows through the transistors, in the off state, that make up the cell. Hence, at any given time, every cell in all but one word line or the entire memory array may not be accessed and subject to leakage power consumption.
Leakage power consumption may include what is commonly referred to as “sub-threshold leakage.” Sub-threshold leakage may refer to the current that flows in the channel of the transistor when the transistor is deactivated, i.e., turned off. Sub-threshold leakage may have an exponential dependency on the threshold voltage divided by thermal energy (kT). Hence, as the threshold voltage is decreased, the sub-threshold leakage is increased. Further, sub-threshold leakage may have a dependency on the channel length. As the channel length of the transistor is decreased, the sub-threshold leakage may be increased.
Sub-threshold leakage has become a major design concern for memory arrays as the transistors in each cell become smaller in size, i.e., as the channel length continues to decrease, due to technological innovations.
Therefore, there is a need in the art to reduce sub-threshold leakage in memory arrays such as SRAM.